The present invention generally relates to semiconductor integrated circuits, and more particularly, to bulk cobalt contact and interconnect structures.
Integrated circuit processing can be generally divided into front end of the line (FEOL), middle of the line (MOL) and back end of the line (BEOL) processes. The FEOL and MOL processing will generally form many layers of logical and functional devices. By way of example, the typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation. Layers of interconnections are formed above these logical and functional layers during the BEOL processing to complete the integrated circuit structure. As such, BEOL processing generally involves the formation of insulators and conductive wiring.
Cobalt is a promising fill material that can be used in FEOL, MOL, and BEOL fabrication processes for advanced semiconductor devices. For example, cobalt can be used as a PMOS fill material in a metal gate, a contact conductor fill, and as a conductor fill material for interconnects.